1. Field of the Invention
The field of the present invention relates to electronic design automation and, more particularly, to methods and systems for constructing integrated circuits and circuit block components using electronic design automation.
2. Background
Chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer builds up a circuit by inputting information at a computer workstation generally having high quality graphics capability so as to display portions of the circuit design as needed. A topdown design methodology is commonly employed using hardware description languages (HDLs), such as Verilog® or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. After this specific cell-to-cell connectivity has been established, the physical design and layout software creates a physical layout file of the integrated circuit, including the physical position of each metal line (i.e., wire) and each via (i.e., metal transition between chip layers). As a last step before creation of the mask file for delivery to the fabrication facility, the physical verification and layout validation software performs several design rule checks (DRCs) on the layout file.
Further explanation of a particular chip design process is set forth, for example, in U.S. Pat. No. 5,838,583, hereby incorporated by reference as if set forth fully herein.
One of the new developments in circuit designs is the advent of so-called virtual component blocks, which, from a general standpoint, are pre-designed and pre-hardened (or semi-hardened) circuit designs in software form (for example, in GDSII format), which can be readily re-used or recycled in different, larger circuit designs. An advantage of virtual component (or VC) blocks is that they reduce the time to design an overall circuit, and thereby increase the speed to market. Virtual component blocks can also be pre-tested and verified from a logical and functional standpoint, also saving time in the test and verification areas.
While virtual component blocks have been found to be advantageous in many contexts, difficulties may be encountered when attempting to define a virtual component block that contains many capabilities yet is sufficiently generic to be used in multiple applications. If too many features are specified, then the virtual component block will be too large for many applications, causing wasted space. On the other hand, if too few features are specified, then very similar additional circuitry will likely be needed in a number of different circuit designs in which the virtual component block is used, resulting in needless duplication of design effort and increased time to reach a final product.
Another problem is that a virtual component block designed to contain the primary processing components of a circuit design may turn out to be rather large, and will often be the largest circuitry block in the circuit design. Such a virtual component block can take up half the available space of an integrated circuit design. Once a large virtual component block is placed in a circuit design, it can be difficult to route a system bus efficiently. It two smaller virtual component blocks are located on opposite sides of a large virtual component block, then the system bus may need to be routed around the large virtual component block, increasing propagation delays and wasting valuable space.
One possible approach to handle such a situation is to place feedthrough wires in a criss-cross pattern within the large virtual component block, to allow signals to pass through the virtual component block if necessary. However, feedthrough wires do not present a very efficient solution to the problem, because the wires are generally too spread out to form a suitable system bus. Moreover, feedthroughs that are not utilized constitute wasted system resources.
Another problem encountered in circuit design in which re-use of pre-established virtual component blocks may be attempted is that the pre-established virtual component blocks are often inflexible or pre-hardened, making layout problematic. If signals between pre-hardened virtual component blocks need to be connected, yet are on opposite sides of each other after placement of the virtual component blocks, then the signal lines (i.e., wires) may be unduly long. Likewise, if signals from a pre-hardened virtual component block needs to be connected to a chip pin not close by, then long signal lines may result. Long signal lines may have undesirable side effects, such as increased signal delay, capacitance, noise and interference. Alternatively, the virtual component blocks may be re-located so that the necessary connections are closer to one another, but then connections to other virtual circuit blocks or chip pins may be made longer.
It would therefore be advantageous to provide techniques to increase flexibility in virtual circuit design, thereby improving convenience and layout particularly of circuit designs incorporating multiple circuit blocks.